Synchronous design allows precise cycle control with the use of system clock.

Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Specifications:

• Description: DDR 400 1GB CL2.5/3 U-DIMM
• Interface: SSTL_2 184 Pin DIMM
• Capacity: 1GB
• Data Transfer Rate: 3.2Gbps
• Power Consumption: 2.5V
• Dimensions: 133.35 x 30 x 3.2 mm (5.25 x 1.18 x 0.13 in)

Other Information:

• JEDEC standard Double Data Rate architecture
• 200MHz clock frequency
• Cas Latency : 2.5 /3
• Serial Presence Detect with EEPROM
• TSOP IC package